Analog-to-difunction converters



May 5, 1959 s. HANSEN ANALOG-TO-DFUNCTIGN CONVERTERS 4 Sheets-Sheet 1Filed Oct. 17, 1955 N .QQ

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May 5,- 1959 s. HANSEN` ANALoG-To-DIFUNCTIQN coNvEr-iTERs 4 Sheets-Sheet2 Filed OCL. 17, 1955 May 5, 1959 s. HANSEN ANALOG-TO-DIF'UNCTIONCONVERTERS Filed Oct. 17, 1955 i l l l l l l l l l Il s. HANSEN2,885,662

ANALOG-TO-DIFUNCTION CCNVERTERS 4 Sheets-Sheet 4 May 5, 1959 Filed OCJC.17, 1955 nited States Patent O W ANALOG-TO-DIFUNCTION CUNVERTERSSiegfried Hansen, Los Angeles, Calif., assignor, by mesne assignments,to Litton Industries, Inc., Beverly Hills, Calif., a corporation ofDelaware Application October 17, 1955, Seal No. 540,699 14 Claims. (Cl.340-347) This invention relates to analog-to-difunction converters andmore particularly to converters which are operative to convert to adifunction output signal train an applied analog signal by integratingthe signal, generating periodic difunction signals corresponding to thevalue of the integral with respect to a reference level, and decreasingthe integral by a fixed amount each time the integral exceeds thereference level.

Relatively recent developments in the field of digital computation havebrought forth a new class of electronic digitalcomputing elements inwhich operations are performed on and in response to what has come to betermed difunction signal trains, as contrasted with the conventionaldigital computing machines which operate upon signals representingweighted binary digits. As will be disclosed in more detail hereinafter,the term difunction signal train refers to a train of signals eachhaving either a first value representing a first number or a secondvalue representing a second number, and is readily distinguished fromsignal trains conventional in prior art computer systems in that all ofthe signals in the difunction signal train having the same valuerepresent identical numbers.

For example, if it is assumed that the algebraic numbers in a difunctionsignal train are plus one and minus one, then each of the signals in thetrain individually represents either a plus one or a minus one,depending on the value of the signal. Stated differently, in adifunction signal train the individual signals are unweighted, eachsignal having equal significance with every other signal. Accordingly, adifunction signal train may be termed a non-numerical representation ofthe quantity which the train represents, since the signals are notWeighted according to any number system, or in other words, have noradix as this term is customarily employed. For purposes of simplicity,it will be assumed hereinafter that the difunction signals generated bythe converters of the invention have a value of either a plus one or aminus one, although it will be later shown that the output signals fromthe identical converters may be considered as representing either a plusone or zero by merely changing the difunction notation.

The representation of physical or mathematical quantities by difunctionsignal trains has been found to be extremely useful both in the solutionof mathematical equations and in the field of automatic control. Someexamples of the application of difunction representation of the solutionof mathematical equations may be found in copending U.S. patentapplication Serial No. 388,780, tiled by Floyd G. Steele on October 28,1953, for Electronic Digital Differential Analyzer, wherein difunctionsignal trains are employed for communicating between the integrators ofa digital differential analyzer, and in copending U.S. patentapplication Serial No. 510,673, filed May 24, 1955 by Floyd G. Steelefor Difunction Computing Elements. Similarly, copending U.S. patentapplication Serial No. 311,609, filed September 26, .1952 by Floyd G.Steele, for Computer and Indicator fiatented May 5, 1959 System,discloses the application of difunction representation to the eld ofprocess control and also discloses electronic computing circuits whichoperate directly to perform mathematical operations by combiningdifunction signals.

The foregoing patent applications disclose structures for adding,subtracting, multiplying, dividing, and integrating difunction signaltrains. However, there has remained a need for new and improved forms ofanalog-todifunction converters in order to fully realize the potentialof difunction computing techniques, especially as applied to the fieldof process control and to the solution of real time problems.

In the past a number of analog-to-difunction converters have beenproposed and constructed for converting to difunction form analogsignals of various types. For exampe, U. S. Patent 2,733,430, issuedJanuary 31, 1956 to Floyd G. Steele for an Angular Quantizer, disclosesan angular quantizer which is operative to generate an output difunctionsignal representative of the rotational rate of an associated shaft.Still other forms of analog-todifunction converters are disclosed incopending U. S. patent application Serial No. 510,736, filed May 24,1955 by Floyd G. Steele for Electronic Digital Computing Systems, whichdiscloses devices for converting analog signals rst to related timeintervals, and then to corresponding difunction signal trains. Althougheach of the foregoing conversion devices has been utilized successfullyin numerous instances, there still remains a need for a relativelysimple circuit which is capable of directly converting analog voltagesor currents into their equivalent difunction form representative of themagnitude and polarity of the analog signals.

The present invention fulfills the aforementioned void in the art byproviding an analog-to-difunction converter which is operable todirectly convert an applied analog signal to an equivalent difunctionsignal train. According to the basic concept of the invention, each ofthe analog-to-difunction converters herein set forth includes anintegrator for integrating the analog quantity with respect to time overeach difunction signal period, a comparator or sensing element operativeto sample the integral developed for generating a plus one representingdifunction signal if the value of the integral exceeds a predeterminedreference level and a minus one representing difunction signal if thevalue of the integral is less than the reference level, and a standardsignal source operable in response to each plus one difunction signalfor subtracting from the integral a unit quantity representative of thedifunction signal generated.

According to several specific embodiments of the invention, theintegrator utilized for integrating the applied analog signal includes acapacitor which is charged during each difunction signal period at arate and in a sense corresponding to the magnitude and polarity of anapplied variable voltage analog signal. The integral signal thusdeveloped is then sampled at the end of each difunction signal period byan associated electronic sensing circuit which in turn generates acontrol signal, corresponding to a plus one representing difunctionsignal, each time the integral exceeds a predetermined referencepotential. Each control signal generated is then employed to control theactuation of a standard charge storage circuit which when actuatedfunctions to discharge the integrator capacitor by a xed amount and in asense opposite to the polarity of the capacitor voltage when last sensedby the sensing element.

It should be pointed out that the term capacitor discharge as hereinemployed does not imply that the capacitor thus operated is driven toground potential, but instead implies that the voltage on the capacitoris driven in a sense opposite to the polarity of the capacitor voltagewhen last sampled. Thus for example, a capacitor which has charged to avoltage of plus one volt may be discharged to a minus two volts, eventhough the final charge on the capacitor is thereby increased over itsinitialvalue if it is assumed that the other terminal of the capacitoris at ground potential.

In accordance with different embodiments of the invention there areprovided an electronic analog-todifunction converter which is operativeto convert a bipolar variable voltage analog signal to its difunctionequivalent, and a modified form of electronic converter which functionsto convert a unipolar analog signal to an equivalent difunction signaltrain. In still another embodiment of the invention there is provided anelectromechanical analog-to-difunction converter for converting to adifunction output signal train an applied mechanical analog signal, thebasic concept and mode of operation of the invention being generic to`both this latter embodiment and the electronic embodiments previouslydescribed.

It is, therefore, an obiect of the invention to provideanalog-to-difunction converters which are operative to directly convertan applied analog signal to an equivalent difunction signal trainnon-numerically representative of the quantity represented by theapplied analog signal.

Another object of the invention is to provide analogto-difunctionconverters which function to convert an applied analog signal to anequivalent difunction signal train by integrating the applied signal,periodically sampling the applied signal to generate difunction signalscorresponding to the value of the integral with respect to apredetermined reference level, and decreasing the integral by apredetermined fixed quantity corresponding to value of the difunctionsignal each time the signal exceeds the reference level.

A further object of the invention is to provide electronicanalog-to-difunction converters which function to convert an appliedvariable voltage analog signal to its equivalent difunction form byintegrating the signal with respect to time during each successivedifunction signal period, sampling the integral signal at the end ofeach period to generate a difunction signal having one value each timethe integral signal exceeds a predetermined reference voltage, anddecreasing the integral signal by a xed amount each time a difunctionsignal having said one value is generated.

Still another obiect of the invention is to provide electronicanalog-to-difunction converters for converting an applied electricalanalog signal to an equivalent difunction signal train, the convertersincluding a capacitor for developing a charge corresponding to theintegral with respect to time of the analog signal, and being operativeto generate a difunction signal representative of a predeterminednumerical value each time the capacitor charges above a predeterminedvalue and to discharge the capacitor with a predetermined standardcharge each time a difunction signal having said predetermined value isgenerated.

The novel features which are believed to be characteristic of theinvention, both as to its organization and method of operation, togetherwith further obects and advantages thereof, will be better understoodfrom the following description considered in connection with theaccompanying drawings in which several embodiments of the invention areillustrated by way of example. lIt is to be expressly understood,however, that the drawmgs are for the purpose of illustration anddescription only, and are not intended as a delinition of the limits ofthe invention.

Fig. 1 is a block diagram illustrating the basic elements of theanalog-to-difunction converters of the invention; Fig. 2 is a circuitdiagram, partly in schematic form, of an electronic analog-to-difunctionconverter, according to the invention;

Figs. 3a, 3b and 3c are waveforms illustrating the operation of thecircuit of Fig. 2;

Fig. 4- is a schematic diagram of a modified standard signal sourcewhich may be employed in the embodiment of Fig. 2;

Fig. 5 is a schematic diagram of a combined integrator and instrumentcircuit which may be employed in the circuit of Fig. 2 for generating adifunction output signal train representative of an analog inputcurrent;

Fig. 6 is a circuit diagram, partly in schematic form, of a modifiedelectronic analog-to-difunction converter, according to the invention;

Figs. 7a and 7b are waveforms illustrating the operation of the circuitof Fig. 5; and

Fig. 8 is a block diagram, partly in schematic form, of anelectromechanical analog-to-difunction converter in accordance with theinvention.

With reference now to the drawings, wherein like or corresponding partsare designated by the same reference characters throughout the severalviews, there is shown in Fig. 1 a block diagram of the basicanalogto-difunction converter of the invention which is operative toproduce at an output terminal 10 a difunction output signal trainnon-numerically representative of the magnitude and polarity of ananalog input signal applied to an input terminal 12. As shown in Fig. 1the converter is operated in synchronism with a timing signal source 14which generates a periodically recurring clock or timing signal (tp)which delimits or marks oi successive difunction signal periods, andincludes three basic elements, namely, an integrator 16 which integratesthe applied analog signal with respect to time over each difunctionsignal period, a sensing element 18 coupled to the integrator andoperative to sample the integral developed during each difunctioninterval for generating a plus one representing difunction signalwhenever the integral exceeds a predetermined reference level, and astandard signal source 20 coupled to the sensing element and operativein response to each plus one representing difunction signal forsubtracting a predetermined xed quantity, representative of a plus onedifunction signal, from the integral developed by integrator 16.

Consider now the basic mode of operation of the analog-to-difunctionconverter of Fig. 1. It will be assumed that initially integrator 16 hasan initial remainder (RO) stored therein, and that the analog inputsignal is thereafter integrated through a difunction signal period,after which sensing element 18 compares the integral developed with areference level (L) to determine whether a plus one or minus onedifunction signal should be generated. Thus the sign of the difunctionsignal may be expressed as:

sign of (RO-l-AQO) --L=sign of difunction signal No. l

where X1 takes the value of the difunction signal generated, namely plusone.

During the succeeding difunction signal period the integration processis again carried out and an incremental integral AQ; is added to theremainder R1. Consequently the sign of (R14-AQ1)-L=sign of difunctionsignal No. 2 (3) Assume now that the second difunction signal has anegative sign. The operation of the analogfto-difunction converter nowmay follow either of two courses, dependpolar analog signals, the newremainder R2 is merely:

(R1+AQ1)=R2 (4) and integrator 16 continues to integrate the appliedsignal through the third difunction signal interval, after which theinterval is again sampled to see if it exceeds level (L). In otherwords, lif the converter is for converting unipolar analog signals totheir difunction equivalents, the value of the integral developed is setback or decreased -When a plus one difunction signal is generated, butis permitted to increase if the level (L) is not exceeded, in whichinstances minus one representing difunction signals are generated. Thusthe sign of the third difunction signal may be expressed as:

sign of (R2+AQ2)=sign of difunction signal No. 3 (5) if, on the otherhand, the analog to diftmction converter is to be capable of convertingbipolar signals to difunction form, the xed quantity Qs is added to theintegral developed at the end of each difunction interval during whichthe value of the integral remains less than the reference level L.Consequently the remainder R2 in the bipolar system is:

(R1+AQ1-X2QS)=R2 (6) where X2 takes the value of the difunction signalgenerated, namely minus one.

Generalizing the foregoing equations for converters of both bipolar andunipolar analog signals, the sign of the nth difunction signal generatedis given by:

sign of (R 1+AQ 1)-L=sign of nth (7) difunction signal and the remaindermay be expressed as:

Rn:(Rn-li`AQn-1) Qs (8) where X in the case of a converter of bipolarsignals takes the value of the last difunctional signal generated, andin the case of a converter of unipolar analog signals is either a plusone or a zero, depending upon whether a plus one or minus one difunctionsignal was last generated.

If now the terms of Equation 8 are summed over all of the difunctionintervals from the iirst to the nth, there is obtained:

n n-l n-l 'n ZR=ZR+ZAQQL2X (9) which simplifies to rrL-l n RfrRiFAQ-QHEX(10) Since Qs is a standard signal representing unity, the followingexpression may be obtained by transposing terms and dividing all termsby n Consider now the signicance of this equation. be shown that theterm It may jv difference by the total number of signals occurringwithin the interval. In a similar manner, the term n-l 2A@ may be shownto be the integral of the analog divided by the number of difunctionsignal periods, or in other words, to be the average value of the analoginput function over the total interval. Finally, the term it may beshown that the maximum error which can result is It will be recognizedthat regardless of whether the analog-to-difunction converter of theinvention is employed for converting either a bipolar or unipolar analogsignal, if the analog signal is to be representable over its entirerange by an equivalent difunction signal train then the maximumincremental integral which may be generated during any difunctionalsignal period should not exceed the standard unit quantity Qs by whichthe integral stored in integrator 16 is modiable. More specitically, inconstructing an analog-to-difunction converter in accordance with theteachings herein set forth, the standard signal source is preferablydesigned to provide a standard signal equal to the incremental integralsignal which is generated when the analog signal is at its maximumvalue.

With reference now to Fig. 2, there is shown one embodiment of anelectronic analog-to-difunction converter, according to the invention,which is operative to present at output terminal 10 a difunction signaltrain representative of the Value of a bipolar analog signal E which isapplied to a pair of input terminals 12, one of which is grounded. Asshown in Fig. 2, integrator 16 here includes a capacitor 22 and acharging resistor 24 in series therewith, while sensing element 18comprises a direct current amplier 26, which may be chopper stabilizedif desired, a bistable multivibrator or ip-op 28, and a pair of twoinput terminal and gates 30 and 32 which are operative under the controlof amplifier 26 and in response to the timing signal (tp) forcontrolling the conduction state of ip-flop 28.

Before continuing further with the description of the invention,consideration will be given to the designation of the input and outputconductors of ip-op 28. The flip-ilop indicates a pair of inputconductors which are designated the S input conductor and Z inputconductor respectively and a pair of output conductors one of which isdesignated +1 conductor while the other is designated -1 conductor.

In operation flip-flop 2S will be assumed to be responsive to theapplication of an input signal to its S input conductor for setting to aconduction state corresponding to the difunction value of +1, and to theapplication of an input signal to its Z input conductor for setting tothe opposite conduction state, which corresponds to the difunction valueof -1. In addition it will be assumed that when the tlip-tlop is in its+1 representing state the voltage presented on its correspondinglydesignated output conductor has a relatively high level value while thevoltage presented on its -1 conductor has a relatively low level value.Conversely, when the ip-op is in its -1 representing state the voltagepresented on the correspondingly designated output conductor has arelatively high level value whereas the voltage presented on the +1conductor has a relatively lowv level value.

Each and gate is represented in the drawings by a semicircular hood witha dot in the center thereof and may utilize either vacuum tubes orcrystal rectiers, the gates preferably being structurally similar to thegating circuits illustrated in the article entitled How an ElectronicBrain Works by Berkeley and Jensen, found on page 45 of the September1951 issue of Radio-Electronics magazine. Briey stated, each and gateherein disclosed includes two input terminals and a single outputterminal and is responsive to the voltage levels of the signals appliedto its input terminals for presenting at its output terminal the timingpulse applied to one of its input terminals only when the signal appliedto the other input terminal is at its high level value.

Continuing with the description of Fig. 2, standard signal source 20 inthis particular embodiment of the invention comprises a pair of relaysgenerally designated 34 and 36, respectively, a pair of and gates 38 and40 operative under the control of flip-flop 28 and in response to adelayed timing pulse signal received from a delay unit 41 forcontrolling the actuation of the relays, and a standard charge storagecapacitor 42 which is employed in conjunction with relays 34 and 36 forperiodically discharging integrator capacitor 22 under the control ofsensing circuit 18. Referring now with particularity to the circuit ofstandard signal source 20, relay 34 includes a pair of armatures 44 and46 across which capacitor 42 is connected, each of these armatureshaving an associated back contact correspondingly designated with thereference letter a and an associated front Contact designated with thereference letter b. In a similar manner, relay 36 includes a singlearmature 48 having an associated back contact 48a and an associatedfront contact 48b. As shown in Fig. 2, contacts 44h and 46a of relay 34are grounded, while contacts 44a and 46b of relay 34 are respectivelyconnected to amature 48 and Contact 48b of relay 36. Front contact 48aof relay 36, on the other hand, is connected to one terminal Es of astandard voltage source, not shown, through a current limiting resistor50. The circuit of standard signal source 20 is completed through afeedback connection including a current limiting resistor 52 whichinterconnects relay contacts 46a and 48h with the junction of capacitor22 and resistor 24 in integrator circuit 16.

It will be noted that when relays 34 and 36 are in their normalpositions as shown in the drawing, standard charge storage capacitor 42is connected across the standard voltage ES. Consequently, if it isassumed that the value of limiting resistor is relatively small and thatthe standard voltage ls is positive, it will be recognized that apositive standard charge QS is stored in capacitor 42 during eachdifunction signal period, the charge being given by where Cs is thecapacitance of capacitor 42.

If it is now assumed that integrator capacitor 22 is very large comparedto standard charge storage capacitor 42, and that the voltage standardEs is correspondingly large relative to the normal peak signal voltageacross capacitor 22, it is clear that operation of relay 36 willfunction to discharge integrator capacitor 22 in a positive direction byvirtue of a transfer of substantially all of the standard charge oncapacitor 42. Conversely, if relay 36 remains normal and relay 34 isactuated, the polarity of the charge on capacitor 42 is reversed withrespect to ground potential and integrator capacitor 22 will bedischarged in a negative direction by a transfer of the charge oncapacitor 42.

Consider now the interaction of integrator circuit 16 andstandard signalsource 26. It will be recalled that the maximum incremental integral(AQ) which may be developed by the integrator during any one difunctionsignal period cannot exceed the standard integral Qs. Stated in terms ofthe specific circuit of Fig. 2, therefore, the voltage change acrosscapacitor 22 during any one difunction signal period should be incapableof exceeding the standard correction or neutralization voltagecontributed by standard signal source 20 through the aforementionedcapacitive charge transfer.

It may be shown that if an accuracy of the order of one part in onethousand is desired for the analog-todifunction converter of theinvention, then the maximum integral signal AQ which may be generated inany one difunction period should be limited to approximately onethousandth of the maximum value of the analog input signal. In otherWords, if the analog signal were to be variable over a range of i volts,then the maximum integral signal which may be generated over difunctionsignal period should be .1 volt. This parameter of the system of course,is easily controlled by selecting a sutilciently large charging resistor24 and capacitor 22. It may be shown that the charging time constant(RC) for the above voltage range is RC=T/.00l0l (13) where T is thedifunction signal period R is the resistance of resistor 24 and C is thecapacitance of capacitor 22.

It should also be pointed out that for maximum accuracy the chargingtransient of capacitor 22 should be substantially linear and of constantslope for a constant amplitude input signal, or in other words, shouldbe dependent only on the magnitude of the analog signal and should besubstantially independent of the initial voltage across the capacitor.

This requirement is inherently fulfilled in the present invention byvirtue of two facts. Firstly, as set forth hereinabove, the timeconstant of the charging circuit for capacitor 22 is much larger thanthe difunction signal period. Secondly, the converter is essentially anull seeking system which tends to keep the capacitor voltage at apredetermined reference level, the level in the embodiment of Fig. 2being ground potential. Consequently the charging current which isintegrated by capacitor 22 is substantially independent of the initialcharge on capacitor 22; hence the incremental integral signal AQ isdependent only upon the analog signal E, and may be expressed by thefollowing equation:

T, E T E novel) tdt-EL @zt-EXR Since the capacitance (C) of capacitor 22is constant, the incremental integral signal may be considered as thevoltage increase AE across the capacitor, rather than the net chargeincrease. Thus the net voltage change from the integration is:

Q sC+C's If now the value of the standard voltage is 100 volts, for

example, while the capacitance (C) of capacitor 22 is one thousand timeslarger than the capacitance (Cs) of AE,=E (16) capacitor 42, then fromEquation 16 the standard vonage change AE, which may be effected by acharge transfer between capacitors 42 and 22 is .1 volt; this value willin turn be recognized as the maximum incremental voltage change which isproduced across integrator capacitor 22 when the analog input signal Eis at the limit of its range, namely plus or minus 100 volts.

Consider now the operation of the analog-to-difunction converter of theinvention. With reference now to Figs. 3a, 3b and 3c, there areillustrated the waveforms which appear across capacitor 22 for analoginput signals of various magnitudes and polarities. In each of thesefigures there is shown a pair of dotted lines 54 and 56 which representthe threshold voltages at the input to D.C. amplifier 26 below which theoutput signals from the amplifier are insuliicient to open and gates 30and 32 in Fig. 2.

lt will be recalled that for the particular embodiment of Fig. 2, thepredetermined reference level about which the voltage across capacitor22 should vary is ground potential. Ideally, therefore, the thresholdlevels 54 and 56 should both coincide with ground potential. As a matterof practical circuitry, however, some finite voltages of the order ofseveral millivolts above and below ground potential are required beforethe D.C. amplifier is operative to open an and gate so that flip-op 28may be triggered by the timing pulse (tp). For purposes of illustrationthe threshold voltages are exaggerated in the drawings so that theireffect on the operation of the converter can best be described.

Since the actuation of standard signal source 20 is coutrolled fromiiip-liop 28, and since the flip-flop will remain in its existingconduction state if no input pulse is received from either gate 30 orgate 32, it will be recognized that the charge transfer which takesplace at the end of a selected difunction signal period will be in thesame sense as that of the preceding period if at the end of the selectedperiod tfhe voltage across capacitor 22 is within the bounds ofthreshold levels 54 and 56. Although it may at first appear that asubstantial error might thereby be introduced in theanalog-to-difunction conversion, it may be shown that the maximum errorwhich may be introduced in the generation of n successive difunctionsignals is l/ n. Moreover, it may be shown that as reference levels S4and 56 are brought closer to ground potential, the statisticalprobability of this error being produced at al1 becomes smaller andsmaller.

Referring now with particularity to Fig. 3a, there is shown the waveformacross capacitor 22 when the analog input signal E is zero volts. Asillustrated in Fig. 3a, the voltage across capacitor 22 during the rstdifunction signal period is at a level designated 58 which is abovereference level 54. Consequently, a relatively high level signal isapplied to gate 30 in Fig. 2, and at the end of the first intervaltiming pulse (lp) passes through gate 30 and sets flip-flop 28 to itsplus one representing state. Assuming that the delay provided by delayunit 41 in Fig. 2 is merely sutiicient to permit the switchingtransients in ip-op 28 to take place, the delayed timing pulse is thenpassed through gate 38 and functions t0 pulse relay 34. Actuation of therelay then in turn functions in the manner previously described todischarge integrator capacitor 22 in a negative direction and therebydecreases the voltage across the capacitor by the amount AES, as definedin Equation 16, and drives the capacitor voltage to level 60 shown inFig. 3a.

During the second difunction interval the voltage across capacitor 22again remains substantially unchanged owing to the fact that the valueof the analog signal is zero. Consequently at the end of kthe seconddifunction period iiip-flop 23 is set to its minus one representingstate, relay 36 is actuated, and the voltage across the integratorcapacitor is again restored to level 58. The above described process isthen repeated, the integrator capacitor f l@ being alternatelydischarged positively and negatively by standard signal source 20.

Consider now the signal appearing at output terminal 10. Obviously aslijp-flop 28 is alternately switched to its plus one and minus onerepresenting condition states the output signal appearing at outputterminal 20 will alternately vary between a plus one representing highlevel difunction signal and a minus one representing difunction signal.If the difunction signal train thus generated is evaluated by addingtogether the number of plus one representing signals, subtractingtherefrom the number of minus one representing signals, and dividing thedifference by the total number of signals, it will be seen that thevalue of the output train is zero corresponding to the value of theanalog input signal.

With reference now to Fig. 3b, there is shown the Waveform of thecapacitor voltage for an applied analog input signal of +50 volts, whichrepresents half scale voltage in the positive direction. It will benoted that the incremental increase in voltage AE during each difunctioninterval is equal to one-half the voltage change AEs produced at the endof each difunction interval by the standard signal source. From thedescription set forth hereinabove with respect to the operation of thecircuit of Fig. 2, it will be recognized that at the ends of the eightdifunction intervals shown iiip-ilop 28 is sequentially .set to its +l,+1, +1, +1, +1, +1, -1, and +1 representing states, While relays 34 and36 are correspondingly energized in the sequence 34, 34, 36, 34, 34, 34,36 and 34. Evaluation of the difunction sequence over the eightdifunction periods shown then gives awp-gado:M

which will be recognized as corresponding to the sense of the appliedsignal and the ratio of its amplitude to -full scale voltage in thatsense. It should also be noted that the waveform is cyclicallyrepetitive every four difunction intervals, which is of courseconsistent with difunction notation since one-half is representable infour difunction intervals by three plus ones and one minus one.

Referring now to Fig. 3c, there are shown two Waveforms 62 and 64representing the capacitor voltage under two different conditions for anapplied analog signal of -25 volts. Considering initially waveform 62,it will be noted t'hat at the beginning of the first difunction intervalcapacitor 22 has a slight negative voltage thereacross. This voltageincreases negatively during the first difunction interval, at the end ofwhich the capacitor is discharged positively by a plus one representingdifunction signal. Again at the end of the second and third difunctionintervals capacitor 22 is respectively discharged negatively andpositively, in response to sequential difunction output signals of +1and -l.

Considering now the operation of the converter at the end of the fourthdifunction interval, it will be noted that the voltage across capacitor22 is within the bounds of threshold levels 54 and 56. Accordingly,flip-flop 28 remains in its existing state since both of gates 30 and 32are closed, and the flip-flop is operative to again generate a plus onerepresenting difunction signal notwithstanding the fact that thecapacitor voltage does not exceed the threshold. The converter thenagain reverses the conduction state of flip-flop 28 at the ends of thefifth, sixth and eighth difunction intervals and thereby furthergenerates sequentially a +1, 1, -l and +1 during the fifth to eighthintervals, respectively. Evaluating the difunction output train over theeight intervals thus gives 3(+1)+5(-1)/8=1A which corresponds to thesense and magnitude of the applied signal. It will be noted that at theend of the eighth interval the voltage across capacitor 22 is identicalto the voltage existing at the beginning of the first difunctioninterval. Accordingly, if it is assumed that the `analog input signalremains constant 11 at 25 volts, then waveform 62 will recur every eightdifunction intervals.

The purpose of waveform 64 in Fig. 3c is to illustrate that a difunctionsignal train having the same value over eight difunction signal periodsmay be generated if the initial voltage across capacitor 22 at thebeginning of the first difunction interval is different from the initialvoltage which resulted in the generation of waveform 62. Thus thedifunction signal sequence which produces waveform 64 is 1, +1, 1, +1,1, 1, +1 and 1, which again equals 14. It should again be noted that thevoltage remainder at the end of the eighth interval is identical to thecapacitor voltage at the beginning of the first interval. In addition,it will be noted that the conduction state of flip-op 28 is reversed atthe ends of the second, third, fourth, fifth, seventh and eighthdifunction intervals, but remains the same at the end of the rst andsixth intervals owing to the fact that the capacitor voltage is withinthe threshold boundaries.

Summarizing the operation of the bipolar analog-todifunction converterof Fig. 2, it will be recognized that the converter functions tointegrate the analog signal with respect to time over each difunctionsignal period, to sample the integral developed at the end of eachdifunction period for generating a plus one difunction signal if thevalue of the integral is above a predetermined reference level and aminus one difunction signal if the value of the integral is less thanthe reference level, and to decrease the magnitude of the integral atthe end of each difunction interval by either adding thereto orsubtracting therefrom a standard unit quantity, depending upon whetherthe difunction signal generated was a minus one or a plus one,respectively.

It will be recognized that the analog-to-difunction converter of Fig. 2may be modied in numerous particulars without departing from the spiritand scope of the invention. For example there is shown in Fig. 4 analternate form of standard signal source which may be substituteddirectly in the circuit of Fig. 2. In this particular standard signalsource each of relays 34 and 36 includes only one associated set of makeand break contacts, while two matched capacitors 66 and 68 are providedfor discharging the integrator capacitor by selectively either adding astandard charge or subtracting a standard charge. It will also be notedthat the standard signal source of Fig. 4 utilizes two standard voltagesources +Bs and Es, respectively, both of which have the same magnitude.

In the description of Fig. 2 set forth hereinabove it has been assumedthat the applied analog signal was a variable voltage signal E. However,it should be clear that the electronic analog-to-difuncton converters ofthe invention will operate equally well in response to analog signalswherein the forcing function is electrical current. With reference toFig. 5, for example, there is shown a combined integrator and inputinstrument which may be substituted in the circuit of Fig. 2 forgenerating a difunction output signal train representative of airpressure.

As shown in Fig. 5. the combined circuit includes an integratorcapacitor 22 which is connected in series with an ion chamber generallydesignated 70, the ion chamber being operative to produce in a collectorrod 72 a current proportional to the density of air introduced to thechamber through a static tube 74. The current is produced by thecombined action of a long-life radioactive isotope layer 76 whichfunctions to ionize the gas within the chamber, and a cylindricalaccelerating electrode 78 which functions to drive the ions to the lowerpotential collector rod 72. If it is assumed that the temperature of thechamber is substantially constant and that the radioactive isotope has areasonably long half-life, it is clear that the current collected andthereafter integrated by capacitor 22 is directly proportional to themolecular density of the air within the ion chamber. Consequently theoutput difunction signal train is non-numerically rep# resentative ofthe air pressure being measured by the ion chamber.

It will be noted that the ion chamber of Fig. 5 is essentially aunidirectional device, or in other words, can only charge capacitor 22in one direction. Consequently the output difunction which is producedby the converter of Fig. 2 can only vary between all plus ones,representing full scale current, and alternate plus ones and minus onesrepresenting zero current. It may be seen, therefore, that the effectivebandwidth of the output signal train is halved, since there is no analoginput representable by the difunction signal patterns between zero andall minus ones, which normally represents full-scale in the negativedirection. This problem may be avoided by the utilization of aunidirectional analog-to-difunction converter, one of which will now bedescribed.

Referring now to Fig. 6, there is shown an analog-to` difunctionconverter, according to the invention, which is operative to produce ata pair of output terminals 10 a difunction output signal trainnon-numerically representative of the magnitude of a unipolar analoginput signal E applied to input terminals 12. The basic elements ofintegrator 16 are identical with those shown and described hereinabovewith respect to the embodiment of Fig. 2, and are correspondinglydesignated. However, the component parts of sensing element 18 andstandard signal source 20 are here modified to illustrate alternativestructures which may be employed in electronic embodiments of theinvention.

In the embodiment of Fig. 6 sensing element 18 includes a low-drift A.C.amplifier whose input circuit isr connected to integrator 16 and whoseoutput circuit is coupled through a relatively large capacitor 82 to acathode follower circuit generally designated 84. The cathode followeroutput signal is then applied to one input terminal of a two terminaland gate generally designated 86, the other input terminal of the andgate being utilized for receiving the timing signal (tp) while theoutput circuit of the gate is connected to standard signal source 20.

It should be pointed out that the sensing circuit of Fig. 6 ispreferably employed in those applications where an analog signal isavailable for sampling over only a relative short time of the order ofseconds. In such an application the inherent drift of ampliiier 80 maybe rendered substantially inconsequential by utilizing a switch 8S forclamping the amplifier input and output circuits at predetermined levelsbefore the circuit is actuated to generate a difunction output signaltrain. At the end of the sampling interval switch 88 is then againclosed to reestablish the input and output levels, thereby providing inessence a very low frequency chopper stabilizer in which switch 88functions as a chopper.

The standard signal source 20 of Fig. 6 includes as its principalelements a thyratron tube 90 whose grid circuit receives pulses passedby gate 86 and whose plate is connected in series with a winding 92 of arelay generally designated 94. Coupled in parallel with winding 92 is anoutput transformer 96 having two output windings 97 and 9S which arepoled as shown and which are interrogated once per difunction signalperiod to determine whether a plus one or minus one representingdifunction signal is being generated.

Relay 94 includes mechanically intercoupled armatures 100, 102 and 104,each having a correspondingly designated back contact identified by thesuix letter a, armatures and 102 also including an associated frontcontact identified by the suffix letter b. Armature 104 is connected torelay winding 92 and functions when in its normal position to apply theplate voltage B+ to the thyratron circuit and to open the plat voltagesupply circuit when the thyratron has been fired to actuate relay 94,thereby permitting the thyratron to deionize.

rThe'functions of armatures100 and 102, on the other assignee hand, isto normally connect standard charge capacitor 42 across a standardvoltage source Es through a limiting resistor 50 to thereby permit thestorage in the capacitor of a standard charge, in the same manner aspreviously described for the circuit of Fig. 2. Actuation of the relaythen functions to reverse the ground connection to capacitor 42 and tointerconnect the capacitor 42 with capacitor 22 in integrator 16 througha current limiting resistor 52, thereby providing a means fordischarging capacitor 22 in the negative direction by a xed amountwhenever relay 94 is actuated.

Consider now the operation of the analog-to-difunction converter of Fig.6. After switch 88 is opened to initiate operation of the converter,amplifier 80 serves to apply to gate 86 an amplified signalcorresponding to the voltage across integrator capacitor 22, gate 86being opened to pass the next occurring timing pulse each time thecapacitor voltage exceeds a predetermined reference level. Each timingpulse thus passed functions to trigger the thyratron which in turnactuates relay 94 to both squelch the thyratron and transfer charge tothe integrator for discharging capacitor 22.

Assume now that the analog signal is variable over a range from volts to+100 volts; assume also that the reference level at which gate 86 opensis selected so that if integrator capacitor 22 is charged at its maximumrate, or in other words, if the analog signal is +100 volts, theincremental voltage increase across capacitor 22 through one difunctioninterval is just enough, when amplified by amplifier 80, to open gate86. Obviously then, if an analog signal of zero volts is applied to theintegrator, the capacitor voltage will not increase and gate 86 Will notopen. Accordingly, thyratron 90 will not fire and interrogation ofoutput windings 97 and 98 with suitable pulse gates, not shown, willresult in the generation of a minus one difunction signal during eachand every difunction interval. v

With reference now to Figs. 7a and 7b, there are shown waveforms of theintegrator capacitor voltage for analog input signals of variousmagnitudes. For example, the waveform 106 in Fig. 7a illustrates thecapacitor voltage in response to an input signal of +100 volts, whichwill be remembered as being the upper range of the input signal.Recalling that a signal of this magnitude charges capacitor 22 at itsmaximum rate, and that this rate is sufficient to drive the capacitor tothe predetermined reference level, here designated as L, it will berecognized that an input signal of +100 volts will function to triggerthe thyratron during each difunction time interval. Consequentlyinterrogation of output windings 97 and 98 in Fig. 6 will produce acontinuous train of plus one representing difunction signals.

Consider next the application of an analog signal of +50 volts to theintegrator circuit. The voltage across capacitor 22 will then follow thewaveform designated 108 in Fig. 7a, and will reach the level (L) duringevery other difunction interval. Accordingly the difunction s1gnalsderived by interrogation of output windings 97 and 98 will alternatelyrepresent plus ones and minus ones. In a similar manner the waveforms110 and 112 in Fig. 7b represent the capacitor voltage waveforms inresponse to analog input signals of +6627?, volts and +25 voltsrespectively, the sequential difunction signals thereby generated being1, +1, +1, 1, +1, +1 representing +1/3 for waveform 110, and 1, 1, +1,1, 1, +1, 1, +1 representing 1A for waveform-112.l

It should be emphasized that for the foregoing discussion a normalizeddifunction system has been assumed in which the individual difunctionsignals represent either a plus one or minus one. Thus analog inputs1gnals having values of +100, +50 and 0 volts are represented bydifunction signal trains whose values are +1, and 1, respectively.However, if the difunction notation is changed so that the difunctionsignals represent either a plus one or zero instead of plus one andminus one,

respectively, then the difunction signal trains generated in response toanalog input signals of +100, +50 and 0 volts have values of +1, +1/2,and 0, respectively. It is to be expressly understood that no structuralchanges in the circuit of Fig. 6 are required to achieve this result,but only a change in the numerical significance attnibuted to thedifunction signals of one level.

It should also be pointed out that although the circuit of Fig. 6utilizes transformer 96 for deriving its output intelligenceinformation, the same intelligence information is contained in theoutput signal from and gate S6 in sensing circuit 18. More specifically,the appearance of a timing signal (tp) at the output circuit of gate 86at the beginning of a difunction interval indicates a plus onerepresenting difunction signal for that interval, whereas the absence ofa timing signal indicates either a minus one or zero representingsignal, depending upon whether the converter is to present its outputsignal in a normalized +1, 1 difunction system or in a +1, 0 difunctionsystem.

The speciiic embodiments of the invention thus far described have allbeen electronic devices; however, it will be recalled that the basic andmotivating concept of the invention is equally applicable to mechanical,electromechanical or hydraulic analog-to-difunction converters. Withreference to Fig. 8, for example, there is shown a bipolarelectromechanical analog-to-difunction converter in accordance with theinvention which again includes the three basic components set forth inFig. l, namely an integrator 16 for receiving a mechanical signalrepresented by a displacement F, a sensing element 18 for indicatingwhen the integral developed during a difunction interval exceeds apredetermined reference level and for presenting at a pair of outputterminals 10 a pair of complementary output signals representative ofthe equivalent difunction output signal train, and a standard signalsource 20 operable under the control of the sensing element fordecreasing the value of the integral developed whenever the integralexceeds the predetermined reference level.

Integrator 16 includes a conventional wlieel-and-disk integrator 113,the disk being driven by a motor 114 at a rate (dt) and in synchronismwith timing signal source 14, while the wheel is driven by the disk at arate proportional to the magnitude of the displacement F which positionsthe wheel. The wheel shaft is then applied to one input of aconventional mechanical differential 116 through a suitable reductiongear unit, not shown.

The other input shaft of differential 116 is coupled to the shaft of abidirectional notching motor 118 within standard signal source 20, thenotching motor being operative in response to control signals receivedfrom sensing element 18 for rotating its shaft through a discrete angleeach time the motor is actuated. The output shaft of differential 116,on the other hand, is coupled to sensing element 18 wherein itsrotational position is employed for controlling the actuation of asuitable cornmutator or switching mechanism, such as a toggle switch120.

As shown in Fig. 8 toggle switch 120 includes an armature connected totiming signal source 14 for receiving the timing signal (tp), and a pairof contacts 122 and 124 which are selectively engageable by the armaturein accordance with the rotational position of the output shaft from thedifferential. These contacts are then connected to notching motor 118 sothat the notching motor is operative to rotate a discrete amount in onedirection when contact 122 is engaged by its associated armature and atiming pulse is received, and to rotate a discrete amount in theopposite direction when contact 124 is engaged by the toggle switcharmature and a timing pulse is received.

In operation, if the magnitude of displacement F is zero, then the wheelof integrator 113 is positioned at the center of the disk and hencedifferential 116 receives no rotational input from integrator 113.Accordingly, notching motor 118 will be stepped in one direction duringone difunction interval and in the opposite direction during the nextunder the control of toggle switch 120 which lis reversed each time thenotching motor is reversed.

Assume now that displacement F drives the integrator Wheel to someintermediate point on the associated disk. It will be recognized thatthe output shaft of the diierential will be rotated during eachdifunction interval at a rate proportional to the magnitude of thedisplacement, the angular rotation of the output shaft over thedifunction interval corresponding to the integral with respect to timeof the analog input signal. If the integral exceeds the predeterminedreference level, toggle switch 120 is reversed and notching motor 118 isactivated to compensate for the integral signal generated by driving theoutput shaft in the opposite direction through a discrete angle; thisoperation in turn functions to restore the toggle switch to its originalstate.

The operation of the converter of Fig. 8 during ensuing difunctionintervals is substantially identical with the operation of the bipolaranalog-to-difunction converter of Fig. 2, and the waveforms of Figs. 3a,3b and 3c are equally applicable to the converter of Fig. 8. It shouldbe pointed out that in applying these waveforms to Fig. 8 the ordinaterepresents the rotational position of the output shaft from mechanicaldifferential 116 rather than the voltage across an integrator capacitoras described for Fig. 2.

It is to be expressively understood, of course, that numerous othermodifications and alterations may be made in the analog-to-difunctionconverters herein disclosed without departing from the invention. Forexample, it will be recognized that the electromechanical converter ofFig. 8 may be modified to provide a converter of unipolar signals, inwhich instance the converter would be analogous to the unipolarconverter of Fig. 6. Accordingly it is to be expressly understood thatthe spirit and scope of the invention are to be limited only by thespirit and scope of the appended claims.

What is claimed as new is:

l. An analog-to-difunction converter for converting an applied analogsignal to a difunction output signal train, said difunction signal trainbeing composed of a plurality of bivalued difunction signals havingeither a iirst value representing a irst numerical quantity or a secondvalue representing a second numerical quantity, each of the difunctionsignals in the train having a predetermined period, saidanalog-to-difunction converter comprising: an integrator; means forapplying the analog signal to said integrator, said integrator beingresponsive to the analog signal for producing an integral signalrepresenting the integral with respect to time of the analog signal; asensing element coupled to said integrator and operative to periodicallysample the magnitude of said integral signal once per difunction signalperiod, said sensing element including means for generating an outputdifunction signal representing the rst numerical quantity whenever themagnitude of said integral signal exceeds a predetermined referencelevel and an output difunction signal representing the second numericalquantity whenever the magnitude of said integral signal is less thansaid predetermined level; and a standard signal source coupled to saidintegrator and to said sensing element, said standard signal sourcebeing operable when said sensing element generates a difunction signalrepresenting the first numerical quantity for applying a standard signalto said integrator to decrease the magnitude of said integral signal bya fixed amount corresponding to said standard signal and in a sensecorresponding to the direction of said reference level with respect tosaid integral signal.

2. The analog-to-difunction converter defined in claim l wherein saidstandard signal source further includes means responsive to eachdiunction signal representing 16 the second numerical quantity forapplying to said integrator a standard signal to decrease the magnitudeof said integral signal by a xed amount corresponding to said standardsignal and in a sense opposite to the first named sense.

3. An analog-to-difunction converter for converting an applied analogsignal to a difunction output signal train, said difunction signal trainbeing composed of a plurality of bivalued difunction signals havingeither a first value representing a i'irst numerical quantity or asecond value representing a second numerical quantity, each of thedifunction signals in the train having a predetermined period, saidanalog-to-difunction converter comprising: an integrator; means forapplying the analog signal to said integrator, said integrator beingresponsive to the analog signal for producing an integral signalrepresenting the integral with respect to time of the analog signal; asensing element coupled to said integrator and operative to periodicallysample the magnitude of said integral signal once per difunction signalperiod, said sensing element including means for generating an outputdifunction signal representing the first numerical quantity wheneversaid integral signal is positive with respect to a predeterminedreference level and an output difunction signal representing the secondnumerical quantity whenever the magnitude of said integral signal isnegative with respect to a predetermined level; and means coupled tosaid integrator and operable when said sensing element generates adifunction signal representing the first numerical quantity, fordecreasing the magnitude of said integral signal by a iixed amount andin a negative sense with respect to said reference level.

4. An analog-to-difunction converter for converting an applied analogsignal to a difunction output signal train, said difunction signal trainbeing composed of a plurality of bivalued difunction signals havingeither a first value representing a plus one or a second valuerepresenting a minus one, each of the difunction signals in the trainhaving a predetermined period, said analog-to-difunction convertercomprising: an integrator; means for applying the analog signal to saidintegrator, said integrator being responsive to the analog signal forproducing an integral signal representing the integral with respect totime of the analog signal; a sensing element coupled to said integratorand operative to periodically sample the magnitude of said integralsignal at the end of each difunction signal period for generating a plusone representing difunction signal whenever said integral signal ispositive with respect to a predetermined reference level and a minus onerepresenting difunction signal whenever the magnitude of said integralsignal is negative with respect to said predetermined level; and astandard signal source coupled to said integrator and to said sensingelement, said standard signal source being responsive to each plus onerepresenting difunction signal for decreasing by a iixed amount themagnitude of said integral signal in a sense negative with respect tosaid reference level, and to a minus one representing signal fordecreasing by said xed amount the magnitude of said integral signal in asense positive with respect to said reference level.

5. An electronic analog-to-difunction converter for converting anapplied analog signal to a difunction signal train, said difunctionsignal train being composed of a plurality of bivalued difunctionsignals having either a first value representing a rst numericalquantity or a second value representing a second numerical quantity,each of the difunction signals in the train having a predeterminedsignal period, said analog-to-difunction converter comprising: anintegrator circuit including a capacitor; means for applying the analogsignal to said integrator circuit to vary the charge on said capacitorin accordance with the magnitude of the analog signal and in a sensecorresponding to the polarity of the analog signal; a sensing circuitcoupled to said capacitor, said sensing circuit being operativetoperiodically sample the charge on said capacitor at the end of eachdifunction signal 17 period to produce a control signal whenever thecharge on said capacitor exceeds a predetermined charge in one sense;standard charge storage means; means for establishing a standard chargeon said charge storage means during each difunction signal period; meansresponsive to said control signal for connecting said standard chargemeans to said capacitor for discharging said capacitor through saidcharge storage means to decrease the charge on said capacitor in saidone sense by substantially said standard charge; and means responsive tosaid control signal for presenting a difunction signal having said firstvalue during each difunction signal period after the charge on saidcapacitor has exceeded said predetermined charge and a difunction signalhaving said second value during the other difunction signal periods.

6. An electronic analog-todifunction converter for converting an appliedanalog signal to a difunction signal train, said difunction signal trainbeing composed of a plurality of bivalued difunction signals havingeither a first value representing a first numerical quantity or a secondvalue representing a second numerical quantity, each of the difunctionsignals in the train having a predetermined signal period, saidanalog-to-difunction converter comprising: an integrator circuitincluding an integrator capacitor; means for applying the analog signalto said integrator circuit to vary the charge on said capacitor inaccordance with the magnitude of the analog signal and in a sensecorresponding to the polarity of the analog signal; a sensing circuitcoupled to said capacitor, said sensing circuit being operative toperiodically sample the voltage across said capacitor at the end of eachdifunction signal period to produce a difunction signal representingsaid first value whenever the voltage is positive with respect to apredetermined voltage, and to produce a difunction signal representingsaid second value whenever the voltage is negative with respect to saidpredetermined voltage; standard charge storage means including at leastone capacitor; means for establishing a standard charge on said chargestorage means during each difunction signal period; and means responsiveto difunction signals representing said first value for connecting saidstandard charge means to said integrator capacitor through said chargestorage means to decrease the voltage on said integrator in a negativesense relative to said pre-voltage by a fixed amount corresponding tosaid standard charge.

7. The electronic analog-to-difunction converter of claim 6 whichfurther includes means responsive to each difunction signal representingsaid second value for connecting said standard charge storage means tosaid integrator capacitor for discharging said integrator capacitorthrough said charge storage means in a positive sense relative to saidpredetermined voltage to decrease the voltage on said capacitor by saidfixed amount corresponding to said standard charge.

8. An electronic analog-to-difunction converter for converting anapplied bipolar analog signal to a difunction signal train, saiddifunction signal train being composed of a plurality of bivalueddifunction signals having either a first value representing a plus oneor a second value representing a minus one, each of the difunctionsignals in the train having a predetermined signal period, saidanalog-to-difunction converter comprising: an integrator circuitincluding a capacitor; means for applying the analog signal to saidintegrator circuit to vary the charge on said capacitor in accordancewith the magnitude of the analog signal and in a sense corresponding tothe polarity of the analog signal; a sensing circuit coupled to saidcapacitor, said sensing circuit being operative to periodically samplethe voltage n said capacitor once per `difunction signal period toproduce a plus one representing difunction signal when the capacitorvoltage is positive with respect to a predetermined voltage, and toproduce a minus one representing difunction signal when the capacitorvoltage is negative with respect to said predetermined voltage, standardcharge storage means; means for establishing a standard charge on saidcharge storage means during each difunction signal period; and meansoperable to connect said standard charge means to said capacitor onceper difunction period for discharging said capacitor through said chargestorage means to decrease the voltage on said capacitor ina senseopposite to the sense of said capacitor voltage with respect to saidpredetermined voltage when last sampled, and by a fixed voltagecorresponding to said standard charge.

9. The electronic analog-to-difunction converter defined in claim 8wherein said sensing circuit includes a D C. amplier coupled to saidintegrator and operative to amplify the signal appearing across saidcapacitor, and a flip-flop coupled to said amplifier and beingselectively switchable to either a plus one representing conductionstate or a minus one representing conduction state, and gating meansoperable at the end of each difunction signal period and in response tothe amplified signal Afrom said amplier for switching said flip-flop toits plus one representing state when said capacitor voltage exceeds saidpredetermined voltage and to its minus one representing state when saidcapacitor Voltage is less than said predetermined voltage.

l0. An electronic analog-to-difunction converter for converting anapplied unipolar analog signal to a difunction signal train, saiddifunction signal train being composed of a plurality of bivalueddifunction signals having either a first value representing a plus oneor a second value representing a zero, each of the difunction sign-alsin the train having a predetermined signal period, saidanalog-to-difunction converters comprising: an integrator circuitincluding a capacitor; means for applying the analog signal to saidintegrator circuit to vary the charge on said capacitor in accordancewith the magnitude of the analog signal and in a sense corresponding tothe polarity of the analog signal; a sensing circuit coupled to saidcapacitor, said sensing circuit being operative to periodically samplethe voltage on said capacitor once per difunction signal period toproduce a plus one representing difunction signal when the capacitorvoltage is positive with respect to a predetermined reference level, andto produce a zero representing difunction signal when the capacitorvoltage is negative with respect to said predetermined reference level;standard charge storage means; means for establishing a standard chargeon said charge storage means during each difunction signal period; andmeans operable when said sensing element produces a plus onerepresenting difunction signal for discharging said capacitor bysubstantially said standard charge whereby the voltage across saidcapacitor is decreased by a predetermined amount corresponding to saidstandard charge.

1l. The electronic analog-to-difunction converter defined in claim l0wherein said sensing element includes a low drift A.C. amplifier coupledto said capacitor for producing an amplified signal corresponding to thevoltage appearing across said capacitor, and a gate circuit coupled tosaid amplifier and responsive to said amplified signal for producing anoutput signal when said capacitor voltage exceeds said predeterminedreference level at the end of a difunction signal period.

12. The method of generating a difunction signal train representative ofthe magnitude of an analog signal, each difunction signal in the trainhaving a predetermined period and having either a first valuerepresenting a first number or a second value representing a secondnumber corresponding in magnitude but opposite in sign to said firstnumber, said method comprising the steps of: generating a first signalcorresponding to the integral with respect to time of the analog signal,combining a lstandard signal with the first signal whenever the firstsignal exceeds a predetermined value at the end of a difunction signalperiod to reduce the first signal by substantially the value of thestandard signal, and generating a difunction signal having'said rstvalue during each signal period after the combining step has beenperformed, and a difunction signal having said secondV value during allother signal periods.

13. The method of generating a difunction signal train representative ofthe magnitude of an analog signal, each difunction signal in the trainhaving a predetermined period and having either a first valuerepresenting a rst number or `a second value representing a secondnumber, said method comprising the steps of generating an integralsignal corresponding to the integral with respect to' time of the analogsignal, generating a difunction signalhaving saidrst value when theintegral signal is positive with respect to 'a predetermined referencelevel at the end of ra difunction signal period, and a d1'- functionsignal having said second value when the integral signal is negativewith respect to the reference level at the end of a difunction signalperiod, and reducing the integral signal by a xed amount and in a sensenegative with respect to the reference level each time a difunctionsignal having said rst value is generated.

14. The method defined in claim 13 Which includes the additional step ofincreasing the integral signal by a fixed amount and in a sense positivewith respect to the reference level each time a difunction signal havingsaid second value is generated.

No references cited.

